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Add Altera Modular Dev Kit board
This commit adds the Altera Modular Dev Kit board to the example repo. Signed-off-by: Rod Frazer <rod.frazer@altera.com>
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‎README.md‎

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@@ -28,6 +28,7 @@ The project build instructions are documented [**here**](./documentation/17_buil
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| Repo Directory | Board Info |
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| :--- | :--- |
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| brd_altera_a5e065_premium_es | **Company:** Altera Corporation<br>**Board Name:** Agilex* 5 FPGA E-Series 065B Premium Development Kit<br>**OPN:** DK-A5E065BB32AES1<br>**Comment:** ES device |
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| brd_altera_a5e065_modular_es | **Company:** Altera Corporation<br>**Board Name:** Agilex* 5 FPGA E-Series 065B Modular Development Kit<br>**OPN:** MK-A5E065BB32AES1<br>**Comment:** ES device |
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| brd_arrow_axe5_eagle_es | **Company:** Arrow Electronics, Inc.<br>**Board Name:** Arrow AXE5-Eagle Development Platform<br>**OPN:** AXE5-EAGLE-ES<br>**Comment:** ES device |
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| brd_criticallink_mitysbc_es | **Company:** Critical Link, LLC<br>**Board Name:** MitySBC-A5E Single Board Computer<br>**OPN:** A5ED-B9-C7F-RC-SBC-X<br>**Comment:** ES device |
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| brd_macnica_sulfur_es_125 | **Company:** Macnica, Inc.<br>**Board Name:** Macnica Mpression Sulfur Kit / Type A<br>**OPN:** ALTSULFUR_A5ED065B_E5_ES0_typeA<br>**Comment:** ES device - 125MHz SDM_OSC_CLK |

‎brd_altera_a5e065_modular_es/hw_base/a55_do_create_no_pins_hps.tcl‎

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‎brd_altera_a5e065_modular_es/hw_base/a76_do_create_no_pins_hps.tcl‎

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‎brd_altera_a5e065_modular_es/hw_base/create_quartus_project.tcl‎

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#
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# SPDX-FileCopyrightText: Copyright (C) 2025 Altera Corporation
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# SPDX-License-Identifier: MIT-0
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#
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#
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# This script is created by first going into Quartus and select the menu:
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# Project -> Organize Quartus Prime Settings File
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#
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# Then export the project to TCL:
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# Project -> Generate Tcl File for Project...
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#
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# We then take that TCL file and reformat it for our needs. We discard ancilary
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# settings that are of no real use and we remove all .qsys and .ip references
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# because we will restore those into future project creations as we reconstruct
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# the project from raw source.
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#
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# The default format of the pin assignments may or may not be desirable, it will
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# list all pin locations first followed by all pin instance assignments. If we
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# wish to sort this list placing all assignments for a given pin together, we
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# can do this:
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#
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# Duplicate the original generated TCL file and call it pins_only.tcl. Edit the
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# file to remove all entries but the pin assignments. Also remove any entity
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# references at the ends of any lines, each line should end with the
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# "-to <target>" value. Then we can run this command line to sort the pin
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# assignments:
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#
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# []$ awk '{print $NF,$0}' pins_only.tcl | sort -s -k 1,1 | cut -f2- -d' ' > sorted_pins_only.tcl
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#
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package require ::quartus::project
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set PROJECT_NAME "no_pins_top"
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if [project_exists $PROJECT_NAME] {
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post_message -type error "project already exists..."
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post_message -type error "'$PROJECT_NAME'"
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qexit -error
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}
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project_new $PROJECT_NAME
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name VERILOG_FILE ../hw_base/no_pins_top.v
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
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set_global_assignment -name FAMILY "Agilex 5"
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set_global_assignment -name TOP_LEVEL_ENTITY no_pins_top
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set_global_assignment -name BOARD default
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set_global_assignment -name DEVICE A5ED065BB32AE6SR0
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
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set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ
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set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
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set_global_assignment -name USE_HPS_COLD_RESET SDM_IO10
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set_global_assignment -name USE_CONF_DONE SDM_IO16
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set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
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set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
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set_global_assignment -name USE_PWRMGT_SDA SDM_IO16
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set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ"
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set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON
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set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER
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set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 74
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set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 75
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set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
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set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00
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set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00
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set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00
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set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00
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set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00
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set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
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set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
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set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
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set_global_assignment -name NUMBER_OF_SLAVE_DEVICE 2
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set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
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set_global_assignment -name HPS_DAP_SPLIT_MODE "SDM PINS"
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set_global_assignment -name HPS_DAP_NO_CERTIFICATE on
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set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL
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set_global_assignment -name STRATIX_JTAG_USER_CODE 55555555
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set_global_assignment -name USE_CHECKSUM_AS_USERCODE OFF
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set_global_assignment -name HPS_INITIALIZATION "HPS FIRST"
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set_global_assignment -name QSPI_OWNERSHIP HPS
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export_assignments
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project_close
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‎brd_altera_a5e065_modular_es/hw_base/custom_ip.ipx‎

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<!--
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SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
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SPDX-License-Identifier: MIT-0
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-->
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<library>
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<path path="../../custom_ip/**/*" >
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<tag2 key="COMPONENT_IN_PROJECT" value="true" />
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</path>
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<plugin
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name="DDR4-1600L_800MHz_CL12_alloff_component_1CS_DDP_32Gb_2Gx16.qprs"
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file="../hw_base/DDR4-1600L_800MHz_CL12_alloff_component_1CS_DDP_32Gb_2Gx16.qprs"
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displayName="DDR4-1600L_800MHz_CL12_alloff_component_1CS_DDP_32Gb_2Gx16.qprs"
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version="0.0"
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description=""
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tags=""
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categories=""
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type="com.altera.sopcmodel.util.IElementPresetList"
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subtype=""
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factory="PresetFactory">
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<tag2 key="PRESET_TYPE" value="emif_ph2_phy_arch_fp" />
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</plugin>
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</library>

‎brd_altera_a5e065_modular_es/hw_base/no_pins_top.v‎

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/*
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* SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
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* SPDX-License-Identifier: MIT-0
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*/
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`timescale 1ns/10ps
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module no_pins_top (
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input hps_osc_clk,
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output hps_uart0_TX,
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input hps_uart0_RX,
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output wire emif_hps_emif_mem_0_mem_ck_t,
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output wire emif_hps_emif_mem_0_mem_ck_c,
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output wire [16:0] emif_hps_emif_mem_0_mem_a,
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output wire emif_hps_emif_mem_0_mem_act_n,
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output wire [1:0] emif_hps_emif_mem_0_mem_ba,
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output wire [1:0] emif_hps_emif_mem_0_mem_bg,
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output wire emif_hps_emif_mem_0_mem_cke,
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output wire emif_hps_emif_mem_0_mem_cs_n,
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output wire emif_hps_emif_mem_0_mem_odt,
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output wire emif_hps_emif_mem_0_mem_reset_n,
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output wire emif_hps_emif_mem_0_mem_par,
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input wire emif_hps_emif_mem_0_mem_alert_n,
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input wire emif_hps_emif_oct_0_oct_rzqin,
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input wire emif_hps_emif_ref_clk_0_clk,
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inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_t,
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inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_c,
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inout wire [31:0] emif_hps_emif_mem_0_mem_dq
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);
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no_pins_pd_top hps_system (
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.hps_io_hps_osc_clk (hps_osc_clk),
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.hps_io_uart0_tx (hps_uart0_TX),
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.hps_io_uart0_rx (hps_uart0_RX),
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.emif_bank3a_hps_mem_ck_0_mem_ck_t (emif_hps_emif_mem_0_mem_ck_t),
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.emif_bank3a_hps_mem_ck_0_mem_ck_c (emif_hps_emif_mem_0_mem_ck_c),
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.emif_bank3a_hps_mem_0_mem_a (emif_hps_emif_mem_0_mem_a),
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.emif_bank3a_hps_mem_0_mem_act_n (emif_hps_emif_mem_0_mem_act_n),
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.emif_bank3a_hps_mem_0_mem_ba (emif_hps_emif_mem_0_mem_ba),
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.emif_bank3a_hps_mem_0_mem_bg (emif_hps_emif_mem_0_mem_bg),
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.emif_bank3a_hps_mem_0_mem_cke (emif_hps_emif_mem_0_mem_cke),
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.emif_bank3a_hps_mem_0_mem_cs_n (emif_hps_emif_mem_0_mem_cs_n),
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.emif_bank3a_hps_mem_0_mem_odt (emif_hps_emif_mem_0_mem_odt),
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.emif_bank3a_hps_mem_reset_n_mem_reset_n (emif_hps_emif_mem_0_mem_reset_n),
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.emif_bank3a_hps_mem_0_mem_par (emif_hps_emif_mem_0_mem_par),
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.emif_bank3a_hps_mem_0_mem_alert_n (emif_hps_emif_mem_0_mem_alert_n),
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.emif_bank3a_hps_mem_0_mem_dqs_t (emif_hps_emif_mem_0_mem_dqs_t),
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.emif_bank3a_hps_mem_0_mem_dqs_c (emif_hps_emif_mem_0_mem_dqs_c),
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.emif_bank3a_hps_mem_0_mem_dq (emif_hps_emif_mem_0_mem_dq),
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.emif_bank3a_hps_oct_0_oct_rzqin (emif_hps_emif_oct_0_oct_rzqin),
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.emif_bank3a_hps_ref_clk_clk (emif_hps_emif_ref_clk_0_clk)
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);
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endmodule

‎brd_altera_a5e065_modular_es/images/build_images.sh‎

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#!/bin/bash
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#
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# SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
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# SPDX-License-Identifier: MIT-0
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#
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# change into the directory of this script
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cd $(dirname ${0})
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IMAGE_BUILD_SCRIPTS="
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../../common_images/build_demos_fit_image.sh
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../../common_images/build_jic_image.sh
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../../common_images/create_attribution.sh
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../../common_images/fit_no-pins-demos.its
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../../common_images/fit_lzma-no-pins-demos.its
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../../common_images/jic_no-pins-demos.pfg
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"
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for NEXT in ${IMAGE_BUILD_SCRIPTS:?}
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do
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[ -f "$(basename "${NEXT:?}")" ] || {
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cp -s -t ./ "${NEXT:?}" || { echo "ERROR" ; exit 1 ; }
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echo "Created symbolic link for '$(basename ${NEXT:?})'"
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}
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done
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./build_jic_image.sh || { echo "ERROR" ; exit 1 ; }
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‎brd_altera_a5e065_modular_es/init_hw_build_scripts.sh‎

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#!/bin/bash
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#
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# SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
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# SPDX-License-Identifier: MIT-0
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#
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# change into the directory of this script
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cd $(dirname ${0})
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cp -s \
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-t ./ \
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../common_build_scripts/build_hw.sh \
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../common_build_scripts/check_hw_build.sh \
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../common_build_scripts/create_bitstreams.sh \
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../common_build_scripts/hw_build_dirs.src \
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|| { echo "ERROR" ; exit 1 ; }
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# source the hardware build directories variable declaration
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. ./hw_build_dirs.src
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for NEXT_BUILD_DIR in ${HW_BUILD_DIRECTORIES:?}
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do
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echo "Creating hardware directory: '${NEXT_BUILD_DIR:?}'"
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mkdir "${NEXT_BUILD_DIR:?}" && \
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ln -s \
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../../common_build_scripts/uart0_init_proj.sh \
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./${NEXT_BUILD_DIR:?}/init_proj.sh \
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|| { echo "ERROR" ; exit 1 ; }
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done
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‎brd_altera_a5e065_modular_es/sw_builds/build_bootloaders.sh‎

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#!/bin/bash
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#
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# SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
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# SPDX-FileCopyrightText: Copyright (C) 2025 Altera Corporation
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# SPDX-License-Identifier: MIT-0
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#
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TAG_NAME="QPDS25.1_REL_GSRD_PR"
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# change into the directory of this script
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cd $(dirname ${0})
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# extract the musl compiler if we don't already have it
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[ -d aarch64-linux-musleabi-cross ] || {
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tar xf ../../repo_downloads/aarch64-linux-musleabi-cross.tar.xz \
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|| { echo "ERROR" ; exit 1 ; }
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}
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# configure the cross compile environment
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export CROSS_COMPILE=$(realpath aarch64-linux-musleabi-cross/bin/aarch64-linux-musleabi-)
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export ARCH=arm64
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# verify that the tools we need are available in the environment
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TOOLS_REQUIRED="
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${CROSS_COMPILE:?}gcc \
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git \
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make \
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rsync
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"
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ERROR_DETECTED=0
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for NEXT_TOOL in ${TOOLS_REQUIRED:?}
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do
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type -P "${NEXT_TOOL}" > /dev/null 2>&1 || {
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echo "ERROR: required tool is not avaialble in environment"
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echo "'${NEXT_TOOL}'"
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ERROR_DETECTED=1
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}
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done
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[ ${ERROR_DETECTED} -ne 0 ] && {
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exit 1
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}
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# check if source repos already exists
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[ -d ./arm-trusted-firmware ] && {
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echo "INFO: arm-trusted-firmware directory already exists"
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exit 0
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}
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[ -d ./u-boot-socfpga ] && {
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echo "INFO: u-boot-socfpga directory already exists"
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exit 0
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}
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# build the bootloaders
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tar xf ../../repo_downloads/arm-trusted-firmware-${TAG_NAME:?}.tgz \
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|| { echo "ERROR" ; exit 1 ; }
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mv arm-trusted-firmware-${TAG_NAME:?} arm-trusted-firmware \
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|| { echo "ERROR" ; exit 1 ; }
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tar xf ../../repo_downloads/u-boot-socfpga-${TAG_NAME:?}.tgz \
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|| { echo "ERROR" ; exit 1 ; }
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mv u-boot-socfpga-${TAG_NAME:?} u-boot-socfpga \
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|| { echo "ERROR" ; exit 1 ; }
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cd arm-trusted-firmware || { echo "ERROR" ; exit 1 ; }
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make -j 48 PLAT=agilex5 bl31 || { echo "ERROR" ; exit 1 ; }
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cd ../u-boot-socfpga || { echo "ERROR" ; exit 1 ; }
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make mrproper || { echo "ERROR" ; exit 1 ; }
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make socfpga_agilex5_defconfig || { echo "ERROR" ; exit 1 ; }
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ln -s ../arm-trusted-firmware/build/agilex5/release/bl31.bin \
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|| { echo "ERROR" ; exit 1 ; }
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./scripts/kconfig/merge_config.sh -O ./ ./.config \
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../../../common_sw/u-boot_patches/config-fragment \
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|| { echo "ERROR" ; exit 1 ; }
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PATCH_FILES="
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../../../common_sw/u-boot_patches/include-exports.h.patch \
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../../../common_sw/u-boot_patches/include-configs-socfpga_soc64_common.h.patch \
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../../../common_sw/u-boot_patches/include-_exports.h.patch \
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../../../common_sw/u-boot_patches/examples-standalone-Makefile.patch \
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../../../common_sw/u-boot_patches/examples-Makefile.patch \
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../../../common_sw/u-boot_patches/brd_altera_a5e065_premium_es-arch-arm-dts-socfpga_agilex5_socdk-u-boot.dtsi.patch
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"
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for NEXT_PATCH in ${PATCH_FILES:?}
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do
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patch -p1 \
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-i ${NEXT_PATCH:?} \
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|| { echo "ERROR" ; exit 1 ; }
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done
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ln -s \
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-t ./examples/standalone/ \
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../../../../../common_sw/u-boot_standalone_apps/armv8_regs.c \
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../../../../../common_sw/u-boot_standalone_apps/boot_app.c \
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../../../../../common_sw/u-boot_standalone_apps/cache_regs.c \
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../../../../../common_sw/u-boot_standalone_apps/config_clk.c \
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../../../../../common_sw/u-boot_standalone_apps/emac.c \
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../../../../../common_sw/u-boot_standalone_apps/f2h_bridge.c \
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../../../../../common_sw/u-boot_standalone_apps/f2h_irq.c \
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../../../../../common_sw/u-boot_standalone_apps/f2h_irq_handler.c \
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../../../../../common_sw/u-boot_standalone_apps/f2sdram_bridge.c \
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../../../../../common_sw/u-boot_standalone_apps/h2f_bridge.c \
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../../../../../common_sw/u-boot_standalone_apps/h2f_bridge_def_sub.c \
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../../../../../common_sw/u-boot_standalone_apps/h2f_user_clk.c \
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../../../../../common_sw/u-boot_standalone_apps/help_text.h \
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../../../../../common_sw/u-boot_standalone_apps/hps_gp.c \
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../../../../../common_sw/u-boot_standalone_apps/i2c_bridge.c \
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../../../../../common_sw/u-boot_standalone_apps/lwh2f_bridge.c \
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../../../../../common_sw/u-boot_standalone_apps/lwh2f_bridge_def_sub.c \
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../../../../../common_sw/u-boot_standalone_apps/read_sensors.c \
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../../../../../common_sw/u-boot_standalone_apps/sdm_query.c \
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../../../../../common_sw/u-boot_standalone_apps/spi_bridge.c \
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../../../../../common_sw/u-boot_standalone_apps/standalone_common.h \
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../../../../../common_sw/u-boot_standalone_apps/system_counter.c \
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../../../../../common_sw/u-boot_standalone_apps/uart.c \
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|| { echo "ERROR" ; exit 1 ; }
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ln -s \
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../../../../../common_sw/u-boot_standalone_apps/select_uart1.h \
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./examples/standalone/select_uart.h \
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|| { echo "ERROR" ; exit 1 ; }
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make -j 48 || { echo "ERROR" ; exit 1 ; }
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