Update to QPDS 25.1 tools release

This is a significant update to all hardware and software objects within
this repo as they are all updated to build under the QPDS 2.1 tools
environment.

Some of the more notable changes are listed below:

The following IP cores are updated in the 25.1 tools:

    altera_avalon_sysid_qsys 19.1.8
    altera_i2cslave_to_avlmm_bridge  19.1.6
    altera_msgdma 19.2.5
    altera_s10_configuration_clock 19.1.6
    emif_io96b_hps 3.0.0
    intel_agilex_5_soc 7.0.0
    intel_lw_uart lw_uart 1.0.8
    intel_niosv_c 4.0.0
    intel_onchip_memory 1.4.10

The 25.1 tools introduce a new Quartus project setting that we need to
enable the HPS to acquire ownership of the SDM QSPI flash device:

    set_global_assignment -name QSPI_OWNERSHIP HPS

The Linux kernel build needs to add the following flag to the make
invocation:

    DTC_FLAGS=-@

The Agilex 5 devicetree in the Linux kernel source tree moves the FPGA
region node:

    FROM: target-path = /soc@0/base_fpga_region;
      TO: target-path = /fpga-region;

Some additional devicetree syntax needed to be modified for proper
operation as well. The placement of these properties needed to be
relocated:

    /delete-node/ voltage;
    /delete-node/ temperature;

In 25.1 the H2F bridge hardware design has an HPS IO hash mismatch with
respect to all of the other designs. By placing an AXI4 bridge in front
of the H2F bridge and connecting all of the subordinates to the AXI4
bridge, the HPS IO hash seems to consistently match the hash of the rest
of the designs.

u-boot-socfpga, arm-trusted-firmware and linux-socfpga are updated to
the latest tag, QPDS25.1_REL_GSRD_PR

toybox remains at the latest tag, 0.8.12

In the 6.12-lts kernel, the iommu kernel driver framework does not allow
peripherals to bypass translation as easily as previous kernel releases.
There are a number of ways to work around this, we chose to add
devicetree properties to define iommu-addresses for our reserved memory
buffer so that the kernel will provide a 1:1 physical to logical mapping
for the buffer span. This approach is a little messy as overlays are
added and removed, but it seems to work reliably and consistently.

The devicetree overlays for the f2h_bridge and emac examples are updated
with this property.

The 6.12-lts kernel introduces a new kernel config for the Designware
I2C driver, CONFIG_I2C_DESIGNWARE_CORE, which has been added to our
kernel config.

Signed-off-by: Rod Frazer <rod.frazer@altera.com>

Author: rodfrazer-intel

README.md

@@ -7,7 +7,7 @@
 - **title**: agilex5-demo-hps2fpga-interfaces
 - **source**: GitHub
 - **family**: Agilex 5
-- **quartus_version**: Version 24.3.1 Build 102 01/14/2025 Patches 1.14 SC Pro Edition
+- **quartus_version**: Version 25.1.0 Build 129 03/26/2025 SC Pro Edition
 - **devkit**: Agilex 5 FPGA E-Series 065B Premium Development Kit, and others
 - **device_part**: A5ED065BB32AE5SR0, A5ED065BB32AE4SR0, A5ED065BB32AE6SR0
 - **description**: Agilex 5 HPS-to-FPGA interfaces demos.

brd_altera_a5e065_premium_es/hw_base/a55_do_create_no_pins_hps.tcl

@@ -15,7 +15,7 @@ proc do_create_no_pins_hps {} {
 	# add HDL parameters
 
 	# add the components
-	add_component agilex_5_soc ip/no_pins_hps/agilex_5_soc.ip intel_agilex_5_soc agilex_5_soc 6.0.0
+	add_component agilex_5_soc ip/no_pins_hps/agilex_5_soc.ip intel_agilex_5_soc agilex_5_soc 7.0.0
 	load_component agilex_5_soc
 	set_component_parameter_value ATB_Enable {0}
 	set_component_parameter_value CM_Mode {N/A}
@@ -381,6 +381,7 @@ proc do_create_no_pins_hps {} {
 	set_instantiation_interface_parameter_value hps2fpga combinedIssuingCapability {16}
 	set_instantiation_interface_parameter_value hps2fpga dataCheck {false}
 	set_instantiation_interface_parameter_value hps2fpga enableConcurrentSubordinateAccess {0}
+	set_instantiation_interface_parameter_value hps2fpga isTranslator {false}
 	set_instantiation_interface_parameter_value hps2fpga issuesFIXEDBursts {true}
 	set_instantiation_interface_parameter_value hps2fpga issuesINCRBursts {true}
 	set_instantiation_interface_parameter_value hps2fpga issuesWRAPBursts {true}
@@ -448,6 +449,7 @@ proc do_create_no_pins_hps {} {
 	set_instantiation_interface_parameter_value lwhps2fpga combinedIssuingCapability {16}
 	set_instantiation_interface_parameter_value lwhps2fpga dataCheck {false}
 	set_instantiation_interface_parameter_value lwhps2fpga enableConcurrentSubordinateAccess {0}
+	set_instantiation_interface_parameter_value lwhps2fpga isTranslator {false}
 	set_instantiation_interface_parameter_value lwhps2fpga issuesFIXEDBursts {true}
 	set_instantiation_interface_parameter_value lwhps2fpga issuesINCRBursts {true}
 	set_instantiation_interface_parameter_value lwhps2fpga issuesWRAPBursts {true}
@@ -661,6 +663,7 @@ proc do_create_no_pins_hps {} {
 	set_instantiation_interface_parameter_value f2sdram dfhParameterId {}
 	set_instantiation_interface_parameter_value f2sdram dfhParameterName {}
 	set_instantiation_interface_parameter_value f2sdram dfhParameterVersion {}
+	set_instantiation_interface_parameter_value f2sdram isTranslator {false}
 	set_instantiation_interface_parameter_value f2sdram maximumOutstandingReads {1}
 	set_instantiation_interface_parameter_value f2sdram maximumOutstandingTransactions {1}
 	set_instantiation_interface_parameter_value f2sdram maximumOutstandingWrites {1}
@@ -750,6 +753,7 @@ proc do_create_no_pins_hps {} {
 	set_instantiation_interface_parameter_value fpga2hps dfhParameterId {}
 	set_instantiation_interface_parameter_value fpga2hps dfhParameterName {}
 	set_instantiation_interface_parameter_value fpga2hps dfhParameterVersion {}
+	set_instantiation_interface_parameter_value fpga2hps isTranslator {false}
 	set_instantiation_interface_parameter_value fpga2hps maximumOutstandingReads {1}
 	set_instantiation_interface_parameter_value fpga2hps maximumOutstandingTransactions {1}
 	set_instantiation_interface_parameter_value fpga2hps maximumOutstandingWrites {1}
@@ -884,7 +888,7 @@ proc do_create_no_pins_hps {} {
 	add_instantiation_interface_port io96b0_to_hps io96b0_to_hps_axi4_ch0_arprot axi4_ch0_arprot 3 STD_LOGIC_VECTOR Output
 	add_instantiation_interface_port io96b0_to_hps io96b0_to_hps_axi4_ch0_awprot axi4_ch0_awprot 3 STD_LOGIC_VECTOR Output
 	save_instantiation
-	add_component emif_bank3a_hps ip/no_pins_hps/emif_bank3a_hps.ip emif_io96b_hps emif_bank3a_hps 2.0.0
+	add_component emif_bank3a_hps ip/no_pins_hps/emif_bank3a_hps.ip emif_io96b_hps emif_bank3a_hps 3.0.0
 	load_component emif_bank3a_hps
 	set_component_parameter_value EMIF_PROTOCOL {DDR4_COMP}
 	set_component_parameter_value EMIF_REF_CLK_SHARING {0}
@@ -1059,13 +1063,13 @@ proc do_create_no_pins_hps {} {
 	set_component_sub_module_parameter_value emif_0_ddr4comp TURNAROUND_W2W_DIFFCS_CYC {0}
 	set_component_sub_module_parameter_value emif_0_ddr4comp TURNAROUND_W2W_SAMECS_CYC {0}
 	set_component_sub_module_parameter_value emif_0_ddr5comp ADV_CAL_ENABLE_MARGIN {0}
-	set_component_sub_module_parameter_value emif_0_ddr5comp ADV_CAL_ENABLE_RD_DFE {1}
+	set_component_sub_module_parameter_value emif_0_ddr5comp ADV_CAL_ENABLE_RD_DFE {0}
 	set_component_sub_module_parameter_value emif_0_ddr5comp ADV_CAL_ENABLE_REQ {1}
 	set_component_sub_module_parameter_value emif_0_ddr5comp ADV_CAL_ENABLE_WEQ {1}
-	set_component_sub_module_parameter_value emif_0_ddr5comp ADV_CAL_ENABLE_WR_DFE {1}
+	set_component_sub_module_parameter_value emif_0_ddr5comp ADV_CAL_ENABLE_WR_DFE {0}
 	set_component_sub_module_parameter_value emif_0_ddr5comp ANALOG_PARAM_DERIVATION_PARAM_NAME {}
 	set_component_sub_module_parameter_value emif_0_ddr5comp AXI4_ADDR_WIDTH {31}
-	set_component_sub_module_parameter_value emif_0_ddr5comp AXI4_USER_WIDTH {32}
+	set_component_sub_module_parameter_value emif_0_ddr5comp AXI4_USER_WIDTH {0}
 	set_component_sub_module_parameter_value emif_0_ddr5comp CTRL_AUTO_PRECHARGE_EN {0}
 	set_component_sub_module_parameter_value emif_0_ddr5comp CTRL_DM_EN {0}
 	set_component_sub_module_parameter_value emif_0_ddr5comp CTRL_ECC_AUTOCORRECT_EN {0}
@@ -1104,7 +1108,7 @@ proc do_create_no_pins_hps {} {
 	set_component_sub_module_parameter_value emif_0_ddr5comp MEM_DIE_DQ_WIDTH {16}
 	set_component_sub_module_parameter_value emif_0_ddr5comp MEM_DQ_PER_DQS {8}
 	set_component_sub_module_parameter_value emif_0_ddr5comp MEM_DQ_VREF {46}
-	set_component_sub_module_parameter_value emif_0_ddr5comp MEM_FINE_GRANULARITY_REFRESH_MODE {0.0}
+	set_component_sub_module_parameter_value emif_0_ddr5comp MEM_FINE_GRANULARITY_REFRESH_MODE {0}
 	set_component_sub_module_parameter_value emif_0_ddr5comp MEM_NUM_CHANNELS {1}
 	set_component_sub_module_parameter_value emif_0_ddr5comp MEM_NUM_CHANNELS_PER_IO96 {1}
 	set_component_sub_module_parameter_value emif_0_ddr5comp MEM_NUM_IO96 {1}
@@ -1234,13 +1238,13 @@ proc do_create_no_pins_hps {} {
 	set_component_sub_module_parameter_value emif_0_ddr5comp TURNAROUND_W2W_DIFFCS_CYC {0}
 	set_component_sub_module_parameter_value emif_0_ddr5comp TURNAROUND_W2W_SAMECS_CYC {0}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm ADV_CAL_ENABLE_MARGIN {0}
-	set_component_sub_module_parameter_value emif_0_ddr5dimm ADV_CAL_ENABLE_RD_DFE {1}
+	set_component_sub_module_parameter_value emif_0_ddr5dimm ADV_CAL_ENABLE_RD_DFE {0}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm ADV_CAL_ENABLE_REQ {1}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm ADV_CAL_ENABLE_WEQ {1}
-	set_component_sub_module_parameter_value emif_0_ddr5dimm ADV_CAL_ENABLE_WR_DFE {1}
+	set_component_sub_module_parameter_value emif_0_ddr5dimm ADV_CAL_ENABLE_WR_DFE {0}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm ANALOG_PARAM_DERIVATION_PARAM_NAME {}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm AXI4_ADDR_WIDTH {32}
-	set_component_sub_module_parameter_value emif_0_ddr5dimm AXI4_USER_WIDTH {32}
+	set_component_sub_module_parameter_value emif_0_ddr5dimm AXI4_USER_WIDTH {0}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm CTRL_AUTO_PRECHARGE_EN {0}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm CTRL_DM_EN {0}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm CTRL_ECC_AUTOCORRECT_EN {1}
@@ -1280,7 +1284,7 @@ proc do_create_no_pins_hps {} {
 	set_component_sub_module_parameter_value emif_0_ddr5dimm MEM_DIMM_TYPE {UDIMM}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm MEM_DQ_PER_DQS {8}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm MEM_DQ_VREF {39}
-	set_component_sub_module_parameter_value emif_0_ddr5dimm MEM_FINE_GRANULARITY_REFRESH_MODE {0.0}
+	set_component_sub_module_parameter_value emif_0_ddr5dimm MEM_FINE_GRANULARITY_REFRESH_MODE {0}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm MEM_NUM_CHANNELS {2}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm MEM_NUM_CHANNELS_PER_IO96 {1}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm MEM_NUM_IO96 {2}
@@ -1422,10 +1426,10 @@ proc do_create_no_pins_hps {} {
 	set_component_sub_module_parameter_value emif_0_ddr5dimm TURNAROUND_W2W_DIFFCS_CYC {0}
 	set_component_sub_module_parameter_value emif_0_ddr5dimm TURNAROUND_W2W_SAMECS_CYC {0}
 	set_component_sub_module_parameter_value emif_0_lpddr4 ADV_CAL_ENABLE_MARGIN {0}
-	set_component_sub_module_parameter_value emif_0_lpddr4 ADV_CAL_ENABLE_RD_DFE {1}
+	set_component_sub_module_parameter_value emif_0_lpddr4 ADV_CAL_ENABLE_RD_DFE {0}
 	set_component_sub_module_parameter_value emif_0_lpddr4 ADV_CAL_ENABLE_REQ {1}
 	set_component_sub_module_parameter_value emif_0_lpddr4 ADV_CAL_ENABLE_WEQ {1}
-	set_component_sub_module_parameter_value emif_0_lpddr4 ADV_CAL_ENABLE_WR_DFE {1}
+	set_component_sub_module_parameter_value emif_0_lpddr4 ADV_CAL_ENABLE_WR_DFE {0}
 	set_component_sub_module_parameter_value emif_0_lpddr4 ANALOG_PARAM_DERIVATION_PARAM_NAME {}
 	set_component_sub_module_parameter_value emif_0_lpddr4 AXI4_ADDR_WIDTH {31}
 	set_component_sub_module_parameter_value emif_0_lpddr4 CTRL_AUTO_PRECHARGE_EN {0}
@@ -1523,7 +1527,7 @@ proc do_create_no_pins_hps {} {
 	set_component_sub_module_parameter_value emif_0_lpddr4 MEM_VREF_DQ_X_RANGE {1}
 	set_component_sub_module_parameter_value emif_0_lpddr4 MEM_VREF_DQ_X_VALUE {18.0}
 	set_component_sub_module_parameter_value emif_0_lpddr4 MEM_WLS {1.0}
-	set_component_sub_module_parameter_value emif_0_lpddr4 MEM_WR_POSTAMBLE_CYC {0}
+	set_component_sub_module_parameter_value emif_0_lpddr4 MEM_WR_POSTAMBLE_CYC {1}
 	set_component_sub_module_parameter_value emif_0_lpddr4 NUM_IO96_IN_CHIP {8}
 	set_component_sub_module_parameter_value emif_0_lpddr4 PHY_AC_PLACEMENT {FULL}
 	set_component_sub_module_parameter_value emif_0_lpddr4 PHY_REFCLK_ADVANCED_SELECT_EN {0}
@@ -1572,18 +1576,22 @@ proc do_create_no_pins_hps {} {
 	set_component_sub_module_parameter_value emif_0_lpddr4 TURNAROUND_W2W_DIFFCS_CYC {0}
 	set_component_sub_module_parameter_value emif_0_lpddr4 TURNAROUND_W2W_SAMECS_CYC {0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 ADV_CAL_ENABLE_MARGIN {0}
-	set_component_sub_module_parameter_value emif_0_lpddr5 ADV_CAL_ENABLE_RD_DFE {1}
+	set_component_sub_module_parameter_value emif_0_lpddr5 ADV_CAL_ENABLE_RD_DFE {0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 ADV_CAL_ENABLE_REQ {1}
 	set_component_sub_module_parameter_value emif_0_lpddr5 ADV_CAL_ENABLE_WEQ {1}
-	set_component_sub_module_parameter_value emif_0_lpddr5 ADV_CAL_ENABLE_WR_DFE {1}
+	set_component_sub_module_parameter_value emif_0_lpddr5 ADV_CAL_ENABLE_WR_DFE {0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 ANALOG_PARAM_DERIVATION_PARAM_NAME {}
 	set_component_sub_module_parameter_value emif_0_lpddr5 AXI4_ADDR_WIDTH {32}
 	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_AUTO_PRECHARGE_EN {0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_DM_EN {0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_ECC_AUTOCORRECT_EN {0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_ECC_INLINE_EN {0}
-	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_ECC_RD_LINK_EN {0}
-	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_ECC_WR_LINK_EN {0}
+	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_ECC_RD_LINK_EN_FSP0 {0}
+	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_ECC_RD_LINK_EN_FSP1 {0}
+	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_ECC_RD_LINK_EN_FSP2 {0}
+	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_ECC_WR_LINK_EN_FSP0 {0}
+	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_ECC_WR_LINK_EN_FSP1 {0}
+	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_ECC_WR_LINK_EN_FSP2 {0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_PERFORMANCE_PROFILE {default}
 	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_RD_DBI_EN {0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 CTRL_SCRAMBLER_EN {0}
@@ -1640,6 +1648,7 @@ proc do_create_no_pins_hps {} {
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP0_TWTR_L_NS {12.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP0_TWTR_S_NS {7.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP0_TXP_NS {7.0}
+	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP0_TXSR_NS {388.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP0_TZQPD_NS {5.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP1_CK_FREQ_MHZ {687.5}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP1_CL_CYC {15}
@@ -1666,6 +1675,7 @@ proc do_create_no_pins_hps {} {
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP1_TWTR_L_NS {12.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP1_TWTR_S_NS {7.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP1_TXP_NS {7.0}
+	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP1_TXSR_NS {388.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP1_TZQPD_NS {5.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP2_CK_FREQ_MHZ {687.5}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP2_CL_CYC {15}
@@ -1692,6 +1702,7 @@ proc do_create_no_pins_hps {} {
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP2_TWTR_L_NS {12.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP2_TWTR_S_NS {7.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP2_TXP_NS {7.0}
+	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP2_TXSR_NS {388.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_FSP2_TZQPD_NS {5.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_MINNUMREFSREQ {8192.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_NUM_CHANNELS {2}
@@ -1736,7 +1747,6 @@ proc do_create_no_pins_hps {} {
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_TRPPB_NS {18.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_TSR_NS {15.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_TWR_NS {34.0}
-	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_TXSR_NS {388.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_TZQLAT_NS {30.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_VREF_CA_X_CA_VALUE {50.0}
 	set_component_sub_module_parameter_value emif_0_lpddr5 MEM_VREF_DQ_X_VALUE {24.0}