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docs/user_guide: Update axi dac regmap info
Signed-off-by: Stanca Pop <stanca.pop@analog.com>
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docs/user_guide/ip_cores/axi_dac/index.rst

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@@ -211,6 +211,60 @@ see :ref:`axi_dac dac-channel` section.
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To find the instantiation of this module search for ``up_dac_channel`` inside
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the IP's directory.
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.. _generic-dac-register-access:
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Register access
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The DAC IP supports **16 channels**, numbered from **0 to 15**. The **base
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registers** start at offset ``0x0`` and the **common (global) registers** start
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at address ``0x10``. Each **channel** has its own register block, starting from
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address ``0x100`` (for channel 0). Each subsequent channel is spaced by ``0x10``
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(HDL register address) or ``0x40`` (Software addressing).
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Let's say the DAC IP base address is 0x44A0_0000. Here is how the channel offset
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is computed:
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.. math::
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\text{HDL}_{reg} = 0x100 + (n \times 0x10) \\
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.. math::
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\text{Software}_{addr} = IP_BaseAddr + (\text{HDL}_{reg} << 2) = 0x44A0\_0000 + 0x400 + (n \times 0x40)
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This means the first register's address ( **``CHAN_CNTRL``**) is:
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- For **channel 0**:
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- ``0x0100`` (HDL register)=> ``0x44A0_0400`` (Software addressing)
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- For **channel 3**:
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- ``0x0130`` (HDL register) => ``0x44A0_04C0`` (Software addressing)
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- For **channel 15**:
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- ``0x01F0`` (HDL register) => ``0x44A0_07C0`` (Software addressing)
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If you want to access the **``CHAN_CNTRL_3``** register, its address is:
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- For **channel 0**:
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- ``0x0106`` (HDL register) => ``0x44A6_0418`` (Software addressing)
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- For **channel 5**:
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- ``0x0156`` (HDL register) => ``0x44A6_0558`` (Software addressing)
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In general, the address for the ``CHAN_CNTRL_3`` register of **channel *n*** can be calculated as:
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.. math::
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\text{HDL}_{reg} = 0x100 + (n \times 0x10) + 0x06 \\
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.. math::
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\text{Software}_{addr} = IP_base_addr + 0x400 + (n \times 0x40) + 0x18
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Typical Register Map base addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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