docs/library: Fix ADC/DAC Common & Channel base addresses #1943
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Signed-off-by: Stanca Pop <stanca.pop@analog.com>
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Converting this PR to a draft until we come up with a clear explanation + examples on how the register map should be accessed. |
Signed-off-by: Stanca Pop <stanca.pop@analog.com>
Signed-off-by: Stanca Pop <stanca.pop@analog.com>
Signed-off-by: Stanca Pop <stanca.pop@analog.com>
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Add generic regmap info and references that point to ADC/DAC instructions for register access. Signed-off-by: Stanca Pop <stanca.pop@analog.com>
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| - 0x0000 | ||
| - BASE | ||
| - See the `Base <#hdl-regmap-COMMON>`__ table for more details. | ||
| * - 0x0000 |
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For this IP the default offset was probably 0x1000 => 0x4000 based on https://github.com/analogdevicesinc/hdl/blob/main/library/common/up_dac_common.v#L49
But I would remove the documentation for axi_ad9144, since this ip was replaced with the generic dac_jesd_tpl a long time ago.
The dac_jesd_tpl has this set to 0x0 https://github.com/analogdevicesinc/hdl/blob/main/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v#L214
Older dac ips have this generic 0x4000 offset.
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| The ADC IP supports **16 channels**, numbered from **0 to 15**. The **base | ||
| registers** start at offset ``0x0`` and the **common (global) registers** start |
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I would add here a "*" and give more details below.
Usually the start offset is 0x0, But it can be something lese like in the case of axi_adrv9001 which has two adc_common register spaces.
Same for DAC. It can be 0x0 or something in the interval 0x100 to 0x3F00.
PR Description
Fix the base addresses for the ADC Common, ADC Channel, DAC Common and DAC Channel in the IPs documentation.
PR Type
PR Checklist