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IRISZZWIRISZZW
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pwm_timer: modify interface function and add some control cmds
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
1 parent 29e15fc commit d85205e

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6 files changed

+115
-71
lines changed

6 files changed

+115
-71
lines changed

‎board/iotdk/configs/10/iotdk_hardware.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -47,9 +47,9 @@
4747
/* System clock domains */
4848
#define BOARD_REF_CLK (16000000U)
4949
#define BOARD_DFSS_CORE_CLK (144000000U) /* iotdk DFSS clock (including ARC EM) */
50-
#define BOARD_DFSS_IO_CLK BOARD_REF_CLK /* iotdk DFSS IO peripherals clock */
51-
#define BOARD_DFSS_AHB_CLK BOARD_DFSS_CORE_CLK /* iotdk top-level AHB peripherals clock as DFSS */
52-
#define BOARD_DFSS_APB_CLK BOARD_REF_CLK /* iotdk top-level APB peripherals clock as DFSS */
50+
#define BOARD_DFSS_IO_CLK (BOARD_REF_CLK) /* iotdk DFSS IO peripherals clock */
51+
#define BOARD_DFSS_AHB_CLK (BOARD_DFSS_CORE_CLK) /* iotdk top-level AHB peripherals clock as DFSS */
52+
#define BOARD_DFSS_APB_CLK (BOARD_DFSS_CORE_CLK) /* iotdk top-level APB peripherals clock as DFSS */
5353
#define BOARD_APB_CLK (BOARD_DFSS_APB_CLK) /* iotdk top-level APB peripherals clock */
5454
#define BOARD_SPI_CLK (100000000U) /* iotdk SPI clock*/
5555

‎board/iotdk/drivers/ip/designware/pwm_timer/dw_pwm_timer_obj.c‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -84,19 +84,19 @@ static int32_t dw_pwm_timer_0_close (void)
8484
return dw_pwm_timer_close(&dw_pwm_timer_0);
8585
}
8686
/** DesignWare PWM_TIMER 0 control */
87-
static int32_t dw_pwm_timer_0_control (uint32_t cmd, void *param)
87+
static int32_t dw_pwm_timer_0_control (uint32_t ch, uint32_t cmd, void *param)
8888
{
89-
return dw_pwm_timer_control(&dw_pwm_timer_0, cmd, param);
89+
return dw_pwm_timer_control(&dw_pwm_timer_0, ch, cmd, param);
9090
}
9191
/** DesignWare PWM_TIMER 0 write */
92-
static int32_t dw_pwm_timer_0_write (uint32_t ch, uint32_t mode, uint32_t count_low, uint32_t count_high)
92+
static int32_t dw_pwm_timer_0_write (uint32_t ch, uint32_t mode, uint32_t freq, uint32_t dc)
9393
{
94-
return dw_pwm_timer_write(&dw_pwm_timer_0, ch, mode, count_low, count_high);
94+
return dw_pwm_timer_write(&dw_pwm_timer_0, ch, mode, freq, dc);
9595
}
9696
/** DesignWare PWM_TIMER 0 read */
97-
static int32_t dw_pwm_timer_0_read (uint32_t ch, uint32_t *mode, uint32_t *count_low, uint32_t *count_high)
97+
static int32_t dw_pwm_timer_0_read (uint32_t ch, uint32_t *mode, uint32_t *freq, uint32_t *dc)
9898
{
99-
return dw_pwm_timer_read(&dw_pwm_timer_0, ch, mode, count_low, count_high);
99+
return dw_pwm_timer_read(&dw_pwm_timer_0, ch, mode, freq, dc);
100100
}
101101
/** DesignWare PWM_TIMER 0 interrupt routine */
102102
static void dw_pwm_timer_0_isr(void *ptr)
@@ -118,6 +118,7 @@ static void dw_pwm_timer_0_install(void)
118118
dw_pwm_timer_ctrl_ptr->id = DW_PWM_TIMER_0_ID;
119119
dw_pwm_timer_ctrl_ptr->regs = (DW_PWM_TIMER_REG_PTR)(BASE_ADDR_PWM);
120120
dw_pwm_timer_ctrl_ptr->intno = PWM_TIMER_0_CH_0_INTNO;
121+
dw_pwm_timer_ctrl_ptr->clock = BOARD_DFSS_APB_CLK;
121122
dw_pwm_timer_ctrl_ptr->ch_num = DW_PWM_TIMER_0_CH_MAX_COUNT;
122123
dw_pwm_timer_ctrl_ptr->int_handler = dw_pwm_timer_0_isr;
123124

‎device/ip/designware/pwm_timer/dw_pwm_timer.c‎

Lines changed: 73 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@
3232
#include "arc_exception.h"
3333

3434
#include "dw_pwm_timer.h"
35+
#include "embARC_debug.h"
3536

3637

3738
/** check expressions used in DesignWare PWM_TIMER driver implementation */
@@ -174,7 +175,7 @@ int32_t dw_pwm_timer_close(DEV_PWM_TIMER *pwm_timer_obj)
174175
}
175176

176177
/** Read designware pwm_timer device value */
177-
int32_t dw_pwm_timer_read(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t *mode, uint32_t *count_low, uint32_t *count_high)
178+
int32_t dw_pwm_timer_read(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t *mode, uint32_t *freq, uint32_t *dc)
178179
{
179180
int32_t ercd = E_OK;
180181
DEV_PWM_TIMER_INFO_PTR port_info_ptr = &(pwm_timer_obj->pwm_timer_info);
@@ -187,18 +188,38 @@ int32_t dw_pwm_timer_read(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t *m
187188
DW_PWM_TIMER_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED);
188189
DW_PWM_TIMER_CHECK_EXP((ch >= 0)&&(ch < port->ch_num), E_PAR);
189190

190-
*count_low = dw_pwm_timer_count_get(port, ch);
191-
*count_high = dw_pwm_timer_count2_get(port, ch);
191+
int32_t count_low = dw_pwm_timer_count_get(port, ch);
192+
int32_t count_high = dw_pwm_timer_count2_get(port, ch);
193+
192194
*mode = port->mode[ch];
195+
if (*mode == DEV_PWM_TIMER_MODE_TIMER) {
196+
*dc = 100;
197+
if (count_low != 0)
198+
*freq = port->clock / (count_low*2);
199+
else
200+
*freq = 0;
201+
} else if (*mode == DEV_PWM_TIMER_MODE_PWM) {
202+
if (count_low == 0 && count_high == 0) {
203+
*dc = 0;
204+
*freq = 0;
205+
} else {
206+
*dc = (count_high * 100) / (count_high + count_low);
207+
*freq = port->clock / (count_high + count_low);
208+
}
209+
} else {
210+
*dc = 0;
211+
*freq = 0;
212+
}
193213

194214
error_exit:
195215
return ercd;
196216
}
197217

198218
/** Write designware pwm_timer device value */
199-
int32_t dw_pwm_timer_write(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t mode, uint32_t count_low, uint32_t count_high)
219+
int32_t dw_pwm_timer_write(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t mode, uint32_t freq, uint32_t dc)
200220
{
201221
int32_t ercd = E_OK;
222+
int32_t count, count_high;
202223
DEV_PWM_TIMER_INFO_PTR port_info_ptr = &(pwm_timer_obj->pwm_timer_info);
203224

204225
/* START ERROR CHECK */
@@ -208,33 +229,45 @@ int32_t dw_pwm_timer_write(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t m
208229
DW_PWM_TIMER_CTRL_PTR port = (DW_PWM_TIMER_CTRL_PTR)(port_info_ptr->pwm_timer_ctrl);
209230
DW_PWM_TIMER_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED);
210231
DW_PWM_TIMER_CHECK_EXP((ch >= 0)&&(ch < port->ch_num), E_PAR);
211-
212-
dw_pwm_timer_count_set(port, ch, count_low);
213-
dw_pwm_timer_count2_set(port, ch, count_high);
232+
DW_PWM_TIMER_CHECK_EXP((dc >= 0)&&(dc <= 100), E_PAR);
214233

215234
if (mode == DEV_PWM_TIMER_MODE_TIMER) {
235+
DW_PWM_TIMER_CHECK_EXP(freq > 0, E_PAR);
216236
port->mode[ch] = mode;
237+
238+
count = port->clock / freq;
239+
dw_pwm_timer_count_set(port, ch, count/2);
240+
dw_pwm_timer_count2_set(port, ch, 0);
241+
217242
dw_pwm_timer_timer_enable(port, ch);
218243
dw_pwm_timer_pwm_disable(port, ch);
219244
int_enable(port->intno + ch);
220245
} else if (mode == DEV_PWM_TIMER_MODE_PWM) {
246+
DW_PWM_TIMER_CHECK_EXP(freq > 0, E_PAR);
221247
port->mode[ch] = mode;
248+
249+
count = port->clock / freq;
250+
count_high = (count * dc)/100;
251+
dw_pwm_timer_count_set(port, ch, count-count_high);
252+
dw_pwm_timer_count2_set(port, ch, count_high);
253+
EMBARC_PRINTF("clock = %d, count_low = %d, count_high = %d\r\n",port->clock, count-count_high, count_high);
222254
dw_pwm_timer_timer_enable(port, ch);
223255
dw_pwm_timer_pwm_enable(port, ch);
224256
int_disable(port->intno + ch);
225257
} else if (mode == DEV_PWM_TIMER_MODE_CLOSE) {
226258
port->mode[ch] = mode;
259+
dw_pwm_timer_count_set(port, ch, 0);
260+
dw_pwm_timer_count2_set(port, ch, 0);
227261
dw_pwm_timer_timer_disable(port, ch);
228262
dw_pwm_timer_pwm_disable(port, ch);
229263
int_disable(port->intno + ch);
230264
}
231-
232265
error_exit:
233266
return ercd;
234267
}
235268

236269
/** Control designware pwm_timer device */
237-
int32_t dw_pwm_timer_control(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ctrl_cmd, void *par)
270+
int32_t dw_pwm_timer_control(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t ctrl_cmd, void *par)
238271
{
239272
int32_t ercd = E_OK;
240273
DEV_PWM_TIMER_INFO_PTR port_info_ptr = &(pwm_timer_obj->pwm_timer_info);
@@ -245,53 +278,61 @@ int32_t dw_pwm_timer_control(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ctrl_cmd, vo
245278

246279
DW_PWM_TIMER_CTRL_PTR port = (DW_PWM_TIMER_CTRL_PTR)(port_info_ptr->pwm_timer_ctrl);
247280
DW_PWM_TIMER_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED);
281+
DW_PWM_TIMER_CHECK_EXP((ch>=0)&&(ch<port->ch_num), E_PAR);
248282

249283
DEV_PWM_TIMER_CFG *cfg_ptr;
250-
uint32_t ch;
251284
switch (ctrl_cmd) {
252285
case PWM_TIMER_CMD_SET_CFG:
253286
cfg_ptr = (DEV_PWM_TIMER_CFG *) par;
254-
DW_PWM_TIMER_CHECK_EXP((cfg_ptr->ch>=0)&&(cfg_ptr->ch<port->ch_num), E_PAR);
255287

256-
dw_pwm_timer_count_set(port, cfg_ptr->ch, cfg_ptr->count_low);
257-
dw_pwm_timer_count2_set(port, cfg_ptr->ch, cfg_ptr->count_high);
288+
dw_pwm_timer_count_set(port, ch, cfg_ptr->count_low);
289+
dw_pwm_timer_count2_set(port, ch, cfg_ptr->count_high);
258290
if (cfg_ptr->isr_hander != NULL) {
259-
port->ch_isr->int_ch_handler_ptr[cfg_ptr->ch] = cfg_ptr->isr_hander;
291+
port->ch_isr->int_ch_handler_ptr[ch] = cfg_ptr->isr_hander;
260292
}
261293
if (cfg_ptr->mode == DEV_PWM_TIMER_MODE_TIMER) {
262-
port->mode[cfg_ptr->ch] = cfg_ptr->mode;
263-
dw_pwm_timer_timer_enable(port, cfg_ptr->ch);
264-
int_enable(port->intno + cfg_ptr->ch);
294+
port->mode[ch] = cfg_ptr->mode;
295+
dw_pwm_timer_timer_enable(port, ch);
296+
int_enable(port->intno + ch);
265297
} else if (cfg_ptr->mode == DEV_PWM_TIMER_MODE_PWM) {
266-
port->mode[cfg_ptr->ch] = cfg_ptr->mode;
267-
dw_pwm_timer_timer_enable(port, cfg_ptr->ch);
268-
dw_pwm_timer_pwm_enable(port, cfg_ptr->ch);
298+
port->mode[ch] = cfg_ptr->mode;
299+
dw_pwm_timer_timer_enable(port, ch);
300+
dw_pwm_timer_pwm_enable(port, ch);
269301
} else if (cfg_ptr->mode == DEV_PWM_TIMER_MODE_CLOSE) {
270-
port->mode[cfg_ptr->ch] = cfg_ptr->mode;
271-
dw_pwm_timer_timer_disable(port, cfg_ptr->ch);
272-
dw_pwm_timer_pwm_disable(port, cfg_ptr->ch);
302+
port->mode[ch] = cfg_ptr->mode;
303+
dw_pwm_timer_timer_disable(port, ch);
304+
dw_pwm_timer_pwm_disable(port, ch);
273305
}
274306
break;
275307
case PWM_TIMER_CMD_GET_CFG:
276308
cfg_ptr = (DEV_PWM_TIMER_CFG *) par;
277-
DW_PWM_TIMER_CHECK_EXP((cfg_ptr->ch>=0)&&(cfg_ptr->ch<port->ch_num), E_PAR);
278-
cfg_ptr->count_low = dw_pwm_timer_count_get(port, cfg_ptr->ch);
279-
cfg_ptr->count_high = dw_pwm_timer_count2_get(port, cfg_ptr->ch);
309+
cfg_ptr->count_low = dw_pwm_timer_count_get(port, ch);
310+
cfg_ptr->count_high = dw_pwm_timer_count2_get(port, ch);
280311
if (cfg_ptr->isr_hander != NULL) {
281-
cfg_ptr->isr_hander = port->ch_isr->int_ch_handler_ptr[cfg_ptr->ch];
312+
cfg_ptr->isr_hander = port->ch_isr->int_ch_handler_ptr[ch];
282313
}
283-
cfg_ptr->mode = port->mode[cfg_ptr->ch];
314+
cfg_ptr->mode = port->mode[ch];
284315
break;
285316
case PWM_TIMER_CMD_DIS_CH:
286-
ch = (uint32_t) par;
287-
DW_PWM_TIMER_CHECK_EXP((ch >= 0)&&(ch < port->ch_num), E_PAR);
288317
dw_pwm_timer_timer_disable(port, ch);
289318
break;
290319
case PWM_TIMER_CMD_ENA_CH:
291-
ch = (uint32_t) par;
292-
DW_PWM_TIMER_CHECK_EXP((ch >= 0)&&(ch < port->ch_num), E_PAR);
293320
dw_pwm_timer_timer_enable(port, ch);
294321
break;
322+
case PWM_TIMER_CMD_DIS_ISR:
323+
int_disable(port->intno + ch);
324+
break;
325+
case PWM_TIMER_CMD_ENA_ISR:
326+
int_enable(port->intno + ch);
327+
break;
328+
case PWM_TIMER_CMD_SET_ISR:
329+
DW_PWM_TIMER_CHECK_EXP((par!=NULL) && CHECK_ALIGN_4BYTES(par), E_PAR);
330+
port->ch_isr->int_ch_handler_ptr[ch] = (DEV_PWM_TIMER_HANDLER)par;
331+
break;
332+
case PWM_TIMER_CMD_GET_ISR:
333+
DW_PWM_TIMER_CHECK_EXP((par!=NULL) && CHECK_ALIGN_4BYTES(par), E_PAR);
334+
par = (void *)(port->ch_isr->int_ch_handler_ptr[ch]);
335+
break;
295336
default:
296337
ercd = E_NOSPT;
297338
break;

‎device/ip/designware/pwm_timer/dw_pwm_timer.h‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,7 @@ typedef struct dw_pwm_timer_ctrl {
7777
DW_PWM_TIMER_REG_PTR regs; /*!< pwm_timer port register */
7878
uint32_t intno; /*!< pwm_timer interrupt vector number */
7979
uint32_t ch_num; /*!< pwm_timer group channel count */
80+
uint32_t clock; /*!< pwm_timer clock */
8081
INT_HANDLER int_handler; /*!< pwm_timer interrupt handler pointer */
8182
DW_PWM_TIMER_CH_ISR_PTR ch_isr; /*!< pwm_timer group channel callback pointer */
8283
DEV_PWM_TIMER_MODE_PTR mode; /*!< pwm_timer group channel work mode array pointer*/
@@ -95,9 +96,9 @@ extern "C" {
9596
*/
9697
extern int32_t dw_pwm_timer_open(DEV_PWM_TIMER *pwm_timer_obj);
9798
extern int32_t dw_pwm_timer_close(DEV_PWM_TIMER *pwm_timer_obj);
98-
extern int32_t dw_pwm_timer_read(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t *mode, uint32_t *count_low, uint32_t *count_high);
99-
extern int32_t dw_pwm_timer_write(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t mode, uint32_t count_low, uint32_t count_high);
100-
extern int32_t dw_pwm_timer_control(DEV_PWM_TIMER *pwm_timer_obj, uint32_t cmd, void *param);
99+
extern int32_t dw_pwm_timer_read(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t *mode, uint32_t *freq, uint32_t *dc);
100+
extern int32_t dw_pwm_timer_write(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t mode, uint32_t freq, uint32_t dc);
101+
extern int32_t dw_pwm_timer_control(DEV_PWM_TIMER *pwm_timer_obj, uint32_t ch, uint32_t cmd, void *param);
101102
extern int32_t dw_pwm_timer_isr_handler(DEV_PWM_TIMER *pwm_timer_obj, void *ptr);
102103

103104
#ifdef __cplusplus

‎device/ip/ip_hal/inc/dev_pwm_timer.h‎

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -90,6 +90,14 @@
9090

9191
#define PWM_TIMER_CMD_DIS_CH DEV_SET_SYSCMD(3)
9292

93+
#define PWM_TIMER_CMD_SET_ISR DEV_SET_SYSCMD(4)
94+
95+
#define PWM_TIMER_CMD_GET_ISR DEV_SET_SYSCMD(5)
96+
97+
#define PWM_TIMER_CMD_DIS_ISR DEV_SET_SYSCMD(6)
98+
99+
#define PWM_TIMER_CMD_ENA_ISR DEV_SET_SYSCMD(7)
100+
93101
/** PWM_TIMER interrupt handler or Interrupt Service Routine(ISR) */
94102
typedef void (*DEV_PWM_TIMER_HANDLER) (void *ptr);
95103

@@ -113,7 +121,6 @@ typedef enum dev_pwm_timer_mode {
113121
* PWM_TIMER Device Config Struct
114122
*/
115123
typedef struct dev_pwm_timer_cfg {
116-
uint8_t ch; /*!< conifg channel*/
117124
DEV_PWM_TIMER_MODE mode; /*!< work mode*/
118125
uint16_t count_low; /*!< count for timer or pwm period low*/
119126
uint16_t count_high; /*!< count for pwm period high*/
@@ -133,9 +140,9 @@ typedef struct dev_pwm_timer {
133140
DEV_PWM_TIMER_INFO pwm_timer_info; /*!< PWM_TIMER device information */
134141
int32_t (*pwm_timer_open) (void); /*!< Open pwm_timer device */
135142
int32_t (*pwm_timer_close) (void); /*!< Close pwm_timer device */
136-
int32_t (*pwm_timer_control) (uint32_t cmd, void *param2); /*!< Control pwm_timer device */
137-
int32_t (*pwm_timer_write) (uint32_t ch, uint32_t mode, uint32_t count_low, uint32_t count_high); /*!< Send data by pwm_timer device(blocked) */
138-
int32_t (*pwm_timer_read) (uint32_t ch, uint32_t *mode, uint32_t *count_low, uint32_t *count_high); /*!< Read data from pwm_timer device(blocked) */
143+
int32_t (*pwm_timer_control) (uint32_t ch, uint32_t cmd, void *param2); /*!< Control pwm_timer device */
144+
int32_t (*pwm_timer_write) (uint32_t ch, uint32_t mode, uint32_t freq, uint32_t dc); /*!< Send data by pwm_timer device(blocked) */
145+
int32_t (*pwm_timer_read) (uint32_t ch, uint32_t *mode, uint32_t *freq, uint32_t *dc); /*!< Read data from pwm_timer device(blocked) */
139146
} DEV_PWM_TIMER, * DEV_PWM_TIMER_PTR;
140147

141148

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