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Merge pull request #123 from os-fpga/bug_sim_status
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2 parents c41caca + 2ede58b commit 0d38ca4

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primitive_parser.py

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -314,6 +314,16 @@ def diff_copy_parse(src_path, dest_path):
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old_list = []
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no_tb_list = []
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for prims in new_prim_name_list:
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src_tb = os.path.join(src_path, "..", "tb", prims+ "_tb.v")
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dest_tb = os.path.join(dest_path, "..", "..", "tb", prims.upper(), "")
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# print(", \n\Src path \n\n", src_tb ,", \n\dest path \n\n", dest_tb)
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os.makedirs(dest_tb, exist_ok=True)
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if os.path.exists(src_tb):
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shutil.copy(src_tb, dest_tb)
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# old_prim_set = set(collect_old_primitives(dest_path))
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new_prim_set = set(new_prim_name_list)
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old_prim_set = set(old_prim_name_list)
@@ -367,7 +377,7 @@ def diff_copy_parse(src_path, dest_path):
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if "sim_models" in src_path:
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src = src_path + "../tb"
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dest = dest_path + "../../tb"
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dest = dest_path + "../tb"
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print("Testbench files")
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copy_files(src,dest)
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