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zvfofp4min: fix shared contraint with v[zs]ext
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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riscv/v_ext_macros.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1405,9 +1405,6 @@ VI_VX_ULOOP({ \
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#define VI_EXT_CHECK(div) \
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require(insn.rd() != insn.rs2()); \
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require_vm; \
1408-
reg_t from = P.VU.vsew / div; \
1409-
require(from >= e8 && from <= e64); \
1410-
require(((float)P.VU.vflmul / div) >= 0.125 && ((float)P.VU.vflmul / div) <= 8 ); \
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require_align(insn.rd(), P.VU.vflmul); \
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require_align(insn.rs2(), P.VU.vflmul / div); \
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if ((P.VU.vflmul / div) < 1) { \
@@ -1418,6 +1415,9 @@ VI_VX_ULOOP({ \
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// vector: sign/unsiged extension
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#define VI_VV_EXT(div, type) \
1418+
reg_t from = P.VU.vsew / div; \
1419+
require(from >= e8 && from <= e64); \
1420+
require(((float)P.VU.vflmul / div) >= 0.125 && ((float)P.VU.vflmul / div) <= 8 ); \
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VI_EXT_CHECK(div); \
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VI_LOOP_BASE \
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reg_t pat = (((P.VU.vsew >> 3) << 4) | from >> 3); \
@@ -1466,6 +1466,7 @@ VI_VX_ULOOP({ \
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// for now only support the divisor of two
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#define VI_VF_EXT(div, BODY) \
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require(div == 2 && P.VU.vsew == 8); \
1469+
require(P.VU.vflmul >= 1/4.0); \
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VI_EXT_CHECK(div); \
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VI_LOOP_BASE \
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BODY; \

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