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Pull requests: riscv-software-src/riscv-isa-sim

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Pull requests list

Fix double trap
#2163 opened Nov 26, 2025 by chihminchao Loading…
zvfofp4min: fix shared contraint with v[zs]ext
#2162 opened Nov 26, 2025 by chihminchao Loading…
Enhance zve
#2153 opened Nov 18, 2025 by chihminchao Loading…
FP8 support
#2118 opened Oct 31, 2025 by A-Marcelli Loading…
Implement IMSIC and APLIC
#1999 opened Jun 6, 2025 by i2h2 Loading…
Add feature Smcdeleg
#1913 opened Feb 7, 2025 by JJ-Gaisler Loading…
8 bit floating point
#1910 opened Feb 6, 2025 by rbuchner-aril Loading…
Fix envcfg check when S-mode is not available
#1899 opened Jan 21, 2025 by mimiqdev Loading…
Adding version display option with --version
#1897 opened Jan 20, 2025 by ahmedelalfy94 Loading…
Smcsrind exception fixex
#1896 opened Jan 20, 2025 by JJ-Gaisler Loading…
Fix read value of CSR mip.
#1869 opened Dec 9, 2024 by NewPaulWalker Loading…
Add Shlcofideleg support
#1847 opened Oct 31, 2024 by demin-han Loading…
Fix dtc_output read when interrupted by EINTR
#1801 opened Sep 10, 2024 by MarcoBonino Loading…
README.md: update "Debugging With Gdb"
#1800 opened Sep 9, 2024 by hirooih Loading…
Check tcontrol.mte in trigger_t::allow_action()
#1777 opened Aug 16, 2024 by rtwfroody Loading…
Vector crypto additional
#1748 opened Jul 25, 2024 by nibrunieAtSi5 Draft
hvip: Correct logging value of mip on writing hvip
#1741 opened Jul 23, 2024 by YenHaoChen Loading…
Update mcontrol6 to support version 1.0
#1667 opened May 14, 2024 by rtwfroody Loading…
don't read CSR in csrrw(i) with rd=0
#1628 opened Mar 19, 2024 by ShengMingTangAndes Loading…
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